LeMaker Cello Undead?

“The Cello was announced in early 2016 as a $299 USD developer board with the A1100 ARM 64-bit SoC with four Cortex-A57 cores @ 1.7GHz. The Cello features two DDR3 SO-DIMM slots capable of ECC RAM, two Serial ATA 3.0 ports, Gigabit Ethernet, two USB 3.0 ports, and one PCI Express x16 3.0 slot. There are no integrated graphics, but the PCI-E x16 slot can make for some interesting testing.This board was to begin shipping in Q2’2016, but it and the AMD HuskyBoard never materialized in 2016 and remain largely unavailable to this day. Last month we heard the LeMaker Cello finally shipping to some pre-order customers but on their web-site is listed as “no stock.””
 
See After Years Of Waiting, Hands On With The AMD ARM Board
Yes! After years of waiting, and many long delays, AMD has delivered some A1100-series chips to LeMaker. There is a trickle of “Cello” boards out there and Phoronix got one to test. Quad-core A57 may not sound that great but perhaps the consolation prize will be the chip is the A1170 with eight cores (maybe). It’s hopelessly out of date but it is ARMed and it’s not from Intel. It will have a socket for RAM and sufficient connectivity for my needs. Perhaps it will be a NAS rather than a general server. I still don’t understand why similar boards aren’t pouring forth using the new chips with decent caches…

About Robert Pogson

I am a retired teacher in Canada. I taught in the subject areas where I have worked for almost forty years: maths, physics, chemistry and computers. I love hunting, fishing, picking berries and mushrooms, too.
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131 Responses to LeMaker Cello Undead?

  1. oiaohm says:

    Deaf Spy funny you say terminology you need to go pick up a current x86, avr, pic arm and power cpu manuals and wake up they use different terminology to explain things that what you use.

    CPU architecture and execution pipelines in English?
    https://en.wikipedia.org/wiki/Instruction_pipelining

    The generic execution pipelines is what you see old x86 manuals. Everything else refers to them as instruction pipelines including modern x86 manuals. Please note old you should not use execution pipelines any more as a term.

    Well, it’s a combination of pre-fetching which happens all the time with wide memory and narrow instructions and parallel processing where various choices are executed while decisions are being made in an instruction-pipeline.
    So this by Robert is in fact right.

    Grece you have no protection under Australian deformation law. You are intentionally using a insulting name. So you have to pay me first. So you are a idiot and garbage in the eyes of Australian courts because you are name calling. Its not deformation when what I have called you is true.

    Same goes to deafspy. So as soon as you started name calling you are a idiot/moron/garbage by Australian law. If you want legal protection against those insults you have to use a person proper name/handle/nym. Basically you nave never accepted what you legally to me.

    Remember Grece set a standard so where is DrLoser and Deaf Spy sorry for being wrong. Some how I have multi deformation charges that I can bring against all you idiots but you idiot action have protected me.

  2. Deaf Spy says:

    Now, solar is quite competitive in larger installations without subsidies. Subsidies are in place just to hurry up the process.

    Really. So, according to you, people are forced to pay more expensive electricity, to get cheaper energy faster. Years later this cheaper energy is still not there, and people still pay the more expensive electricity.

    At least you are consistent in your logic. You expect everyone else to work or pay, so that you can get something for free or cheap – be it software, or cheap electricity. Only you don’t get the latter, and I don’t think you ever will.

    Wind is not feasible except in quite windy locations but only on a large scale or right at the load to minimize capital costs

    Well, if the Netherlands (where the wind never stops basically) can’t make these profitable, no one on this planet can.

  3. Deaf Spy wrote, “Fact is that households are still far behind in installing solar panels and wind turbines at their homes. It is a law in Economics theory – if you don’t buy something, it is because you don’t want it hard enough.”

    Nope. Small windmills are very inefficient and high maintenance. They just don’t produce enough power. About half my neighbours use a bit of solar power. It’s just that their homes were built ~20 years ago before solar was feasible. Now, solar is quite competitive in larger installations without subsidies. Subsidies are in place just to hurry up the process. Wind is not feasible except in quite windy locations but only on a large scale or right at the load to minimize capital costs. When I was a boy we had a neighbour who still used a windmill to pump water. A small reservoir was the buffer and the cattle didn’t mind.

  4. Deaf Spy says:

    The price of fuel affects profitability of wind only if utilities haven’t locked in higher prices. Lots of utilities are paying prices negotiated year ago. Further, labour and maintenance and capital costs all affect the price of electricity.

    Thanks for admitting that the financial analysis you referred is incomplete, and that wind utilities rely on anti-market measures to survive. Like state subsidies and state-enforced market for “green” electricity and state-guaranteed high prices of electricity.

    Also, folks want independence from fossil fuels and are willing to pay for that. At some point the price of fuel will be affected by supply and demand for renewables.

    No. It is greenies who want that and might be willing to pay for it, but not necessarily the latter. Common people definitely do not want to pay for it. The evidence? Fact is that households are still far behind in installing solar panels and wind turbines at their homes. It is a law in Economics theory – if you don’t buy something, it is because you don’t want it hard enough.

    Even you still don’t have your famous solar panels.

    Just like you preach for ARM servers you don’t own, like you preach for ARM thin clients you don’t own…

    P.S. Where I live, people are getting fed up paying the “eco” tax in their electricity bills. Times are looming when people would just grab the clubs and run to the nearest solar panel array…

  5. Deaf Spy wrote, “with lower prices of gas and all, windmills are simply cost inefficient, and need subsidies for the state to keep going”.

    The price of fuel affects profitability of wind only if utilities haven’t locked in higher prices. Lots of utilities are paying prices negotiated year ago. Further, labour and maintenance and capital costs all affect the price of electricity. Also, folks want independence from fossil fuels and are willing to pay for that. At some point the price of fuel will be affected by supply and demand for renewables.

  6. Deaf Spy says:

    Well, the Dutch tell exactly the opposite story. Then have lots of windmills (they have windmills even in the sea).

    Now, with lower prices of gas and all, windmills are simply cost inefficient, and need subsidies for the state to keep going. Fact in NL. Not to mention the increasing evidence that they are also green inefficient, too.

    In your paper they make a quite generous estimation of the capacity factor of 34%, too close to the maximum one recorded in Ireland (38.48), while the average is 27,9 and lowest is 19,36. I also see no maintenance costs included in the plan. Risk evaluation is non-existent. In other words, Robert, the financial analysis provided is rather superficial.

  7. Deaf Spy wrote, “Facts in 2003 are better than facts in 2016. Ri-i-i-ight”.

    Yes. Electricity rates have gone up. Profitability is better today, especially for today’s larger turbines.

    See How Profitable are Wind Turbine Projects? An Empirical Analysis of a 3.5 MW Wind Farm In Ireland

    Payback on the investment was less than 7 years.

    It certainly is possible to set up a money-losing wind project but if you need an alternative source of power when the utility is down or the sun doesn’t shine, who cares?

  8. Deaf Spy says:

    Facts in 2003 are better than facts in 2016. Ri-i-i-ight.

  9. Deaf Spy suggested windmills don’t make money.

    However, the facts are different. Even modest operations break even eventually.

  10. Deaf Spy says:

    Btw, very interesting piece of news that should thrill greenies:
    http://nltimes.nl/2016/04/14/hundreds-dutch-green-energy-windmills-operating-loss

    And now, in the land of eternal winds, they scream for increased subsidies.
    Bwa-ha-ha-ha-ha!

  11. Deaf Spy says:

    CPU architecture and execution pipelines in English? These things are not related to locality.

  12. Deaf Spy wrote, “In any professional field, knowing the right terms is the only way to express yourself and understand other’s ideas. And a definite requirement for professionalism.”

    Any what field are you discussing? What language? What locality? We are on the web here and unknown to each other.

  13. Deaf Spy says:

    Huh? Who put you in charge of vocabulary?

    Me? This is terminology we speak of, Robert. In any professional field, knowing the right terms is the only way to express yourself and understand other’s ideas. And a definite requirement for professionalism.

  14. oiaohm says:

    addeq r16,116, # in arm. opps I typo that should be addeq r15,115, # in arm.

  15. oiaohm says:

    Robert Pogson sub r15,r15,#8 refers to jump to address that Deaf Spy could not answer. That is in fact halt and catch fire because that is a never ending loop.

    “how is this phenomenon called, when an instruction after a unconditional jump gets executed?”
    The phenomenon DeafSpy is missing is about out of order execution. There is not enough instructions to work out when the code will execute. First Pentium processor per core is processing 2 instructions at a time current x86 process 3-4 at a time.

    What happens when the cpu hits a slow conditional compare instruction.
    https://iis-people.ee.ethz.ch/~gmichi/asocd/addinfo/Out-of-Order_execution.pdf
    You can end up with a 16 instruction space in x86 between the instructions the cpu is executing.
    Lets add one extra bit to Deafspy code.
    JE #size of jump label#
    JMP label
    MOV r1, 10
    :label

    Yes it possible to use a JE like you use a addeq r16,116, # in arm. This is something that is rare to see in x86 asm but insanely common in arm. Fixed width instruction set means you don’t need to guess instruction sizes so you can just add to the execution point to jump over a branch. Its one of the trouble of those who come to arm of reading the code looking for labels and expect those are the only jump points because that is common x86 and it a conner case on x86 for a jmp to be done without a label but on arm is really common for add and sub jumps to be done without labels.

    B in arm is called branch because it was added latter as the first arm instruction set does not contain branch, First version of arm instruction set jump functions are add, sub and mov. So a branch would be done for a longer jump on arm possible after a conditional add that jumps straight over the branch.

    With that one extra instruction both the JMP to Label and the Mov in a x86 process could be being executed at exactly the same time. After the conditional is resolved the unrequited state in cache is disposed of.

    Robert you are on the right track giving example only of 3 bits of asm close to each other is way too short to guess what order anything happens in. Due to what happens in x86 you have to give atleast 16 instructions on arm with out or order is atleast 12. Now to be able to read the asm and predict 100 percent of the time what order stuff is happening in this is why you need a in-order processor even if it slower than a out of order processor.

    The big thing people miss is once you got out of order you have a commit stage. Until the commit stage you could have multi different possible states in the cpu cache so the cpu may have run instructions from multi branches because is branch prediction did not tell it what way to go so is processed both sides.

    Please note this is not multi cores this is remaining on a single core and single thread.

    Modern out of order cpus really screw with you. So you could have mov instructs two copy time to register under 16 instructions apart and both registers contain the same value because they were executed at exactly the same time and this is x86. This is the reason why you need to use performance counters on x86.

    The idea that you have coded something that will always run single threaded is really out the window on modern day out of order execution cpus.

    Alas, that was beyond Deaf Spy mental abilities.
    So could never write the question right. I think I gave enough clues that he was overlooking something. The sub halt and catch fire instruction was a clue to the problem if Deafspy had looked up how todo that in x86 would have lead to that you could put values into jmp statements to move execution pointer forwards and backwards without a label. So this means his example did not include enough information to be sure that the mov statement was not a jmp in point.

  16. Grece says:

    one of many ways Moore’s Law is used to make life better

    Eh Robert?

    Moore’s Law is a projection and not a physical law. So do tell how it is used to make life better?

  17. DrLoser says:

    It’s also inefficient in that more energy than necessary is expended to do the job …

    O, Dear God in Heaven …

    Let me get this straight, you nincompoop. Even assuming that the minute amounts of energy that are theoretically involved are anything to bother about, do you really believe that more energy is expended, on average, when predictive branching is implemented, than when predictive branching is not implemented?

    Your choice, Bozo. Nincompoop, or not nincompoop.

  18. Grece says:

    The complexity of CPUs these days militates against generic terminology for vastly different technologies. You would need a dozen words just to describe a modern CPU and its processes. One word doesn’t cut it.

    How many people use a dozen words to describe a CPU Robert? I certain it is perhaps a thousand hundred people in that industry.

  19. The Wiz wrote, “in many cases knowing the exact term and the concepts it represents gets you where you need to be technically.”

    Nope. I use that technology. I don’t make it. Also every manufacturer might use different terms even if just to avoid trademarks. The complexity of CPUs these days militates against generic terminology for vastly different technologies. You would need a dozen words just to describe a modern CPU and its processes. One word doesn’t cut it.

  20. wizard emiritus says:

    “Huh? Who put you in charge of vocabulary? Why do I need a word for everything? ”

    Because that’s the way it works in the real world Robert Pogson. Understanding a general concept may help, but in many cases knowing the exact term and the concepts it represents gets you where you need to be technically.

  21. Deaf Spy wrote, “Despite that you also don’t know how this is called”.

    Huh? Who put you in charge of vocabulary? Why do I need a word for everything? I’ve been using computers and microprocessors for many decades. Whether it’s simple gates, various layers of integration or the latest devices, I do understand the process.

  22. Deaf Spy says:

    Thanks, Robert.

    Despite that you also don’t know how this is called, you at least managed to fetch some coherent thoughts on the problem. Alas, that was beyond Fifi’s mental abilities.

    This, Fifi and gentlemen, is called delay slot.

  23. Deaf Spy wrote, “how is this phenomenon called, when an instruction after a unconditional jump gets executed?”

    Well, it’s a combination of pre-fetching which happens all the time with wide memory and narrow instructions and parallel processing where various choices are executed while decisions are being made in an instruction-pipeline. It’s related to out-of-order execution. It’s complexity and one of many ways Moore’s Law is used to make life better. It’s also inefficient in that more energy than necessary is expended to do the job but that’s offset by getting the job done sooner.

  24. Deaf Spy says:

    Don’t be shy Fifi, how is this phenomenon called, when an instruction after a unconditional jump gets executed?

    Robert, care to help your overly challenged friend? You are the only one he has.

  25. Grece threatened legal action.

    Don’t you have to be person or something to do that? You could be a bot. Don’t you need an actual reputation that could be harmed? Taylor Swift just got $1 for winning a groping case. You should reconsider.

  26. Grece says:

    So Grece in my eyes you are total garbage. Sorry I am calling you garbage but you are to much of idiot to get it.

    Well now HamDong, under section 14(2) of the Defamation Act 2005 of Australian law. http://www.austlii.edu.au/au/legis/nsw/consol_act/da200599/s14.html

    I may issue you a Concerns Notice seeking a few options. Namely a complete retraction of what was stated, but I will accept a public apology in lieu.

    There are other alternative options at your disposal:

    1. A letter written by the you, outlining that each statement published is untrue;
    2. A published correction;
    3. A promise not to publish future defamatory statements; or
    4. Compensation. (Note: I would accept payment in Bitcoin)

    If there is no response by you in ten business days. Then I take it that you are in complete disregard of the above law and have no interest in resolving this amicably.

  27. oiaohm says:

    The original question was actually to explain a phenomenon that, in pseudo assembler (I kindly translated it to ARM asm to you) would look like

    Deaf Spy the manual of a arm CPU has what is the pseudo assembler of arm and other fixed width CPUs. Variable width instruction set and Fixed width instruction sets use different pseudo assembler. There is a very big reason because there is a difference in presume when something is fixed and when something is variable encoding.

    So you mistake was translating a variable example to fixed. I need you to ask do you know what sub r15,r15,#8 means. There is something equal in x86 instruction set and if you do it you will open up a conner case in x86 cpu behavior.

    Deaf Spy really tell me the equal to sub r15,r15,#8 in x86 it does exist.

    People who code in fixed width instruction sets are use to seeing a particular conner case as a common event and not a conner case but those who code in variable are not use to seeing it so it a conner case. This is why both fixed and variable pseudo assembler are different because you need to consider them differently. Fixed absolutely no : before or after labels for the pseudo assembler for very good reason.

  28. oiaohm says:

    sub r15,r15,#8
    Deaf Spy what is the above instruction effect on a arm64 cpu?

    Deaf Spy really come on answer it.

    Deaf Spy by the way there is still no one here named Fifi to answer you question. So you have still asked no one. But I have asked you a particular question. If you can say what that is I will answer why you translation to arm from x86 is wrong. There is some interesting B command is not in the first version of the arm instruction set.

  29. Deaf Spy says:

    Fifi, “writeln” is not a question. It is just a reminder that you don’t know anything about anything. Same as the branch-prediction story, where both you and Robert miserably failed.

    The original question was actually to explain a phenomenon that, in pseudo assembler (I kindly translated it to ARM asm to you) would look like:

    ..
    JMP label
    MOV r1, 10
    :label
    ...

    where MOV r1, 10 gets executed.

    Don’t bother answering, Fifi, you can’t, it is obvious from the crap about ARM asm you already wrote. I write this again only to emphasize to Robert that you are a complete ignoramus, a fraud and a liar.

  30. oiaohm says:

    Grece is HamDong. HamDong how are you today?? So Grece in my eyes you are total garbage. Sorry I am calling you garbage but you are to much of idiot to get it.

    sub r15,r15,#8
    Deaf Spy what is the above instruction effect on a arm64 cpu?

    Deaf Spy really come on answer it.

  31. Grece says:

    You could have told the answer instead of just butting in with garbage.

    Why are you calling yourself “garbage” HamDong?

  32. oiaohm says:

    Grece please my question is to Deafspy?

    You could have told the answer instead of just butting in with garbage. Its good to know you are gay Grece since you are the hamdonger here.

  33. Grece says:

    sub r15,r15,#8 = HamDong is gay.

  34. oiaohm says:

    sub r15,r15,#8
    Deaf Spy what is the above instruction effect on a arm64 cpu?

    Deaf Spy really come on answer it.

  35. Grece says:

    Why so salty HamDong? Did your boyfriend cheat on you??

  36. oiaohm says:

    sub r15,r15,#8
    Deaf Spy what is the above instruction effect on a arm64 cpu?

    Deaf Spy really come on answer it.

    You want to claim I did not answer stuff when I did. Please note the lamppost claim of Deafspy exactly matches the person who did that horible attack on youtube. What attempt to recycle old material on me because you cannot come up with anything new.

    Also point cross threads say to me you don’t now the answer to my question.

  37. Deaf Spy says:

    Writeln, Fifi, Writeln.

    But take your meds first. Or did you just had a very rough night under that lamppost? Sad and hard work this is.

  38. oiaohm says:

    wizard emiritus I have no further words for you.
    You said that 5 years ago and never kept to it so I should not expect that now.

  39. oiaohm says:

    Grece there are many people named hamdong. Using it as a insult is really stupid.
    https://hamdong.wordpress.com/

    I am not Hamdong get it into your stupid mind Grece. This is one of these realities.

    Really are you going to say sorry to all the people really named Hamdong that you are wanting to link me to Grece. There are people who use the nym hamdong I never do.

    This is the reality here you are linking me to nym that are not mine.

    What’s wrong with your name HamDong?
    First problem is not any of my names. I have 8 names that are my official handles.

    This is you guys being idiot and associating me with names that are not mine to be associated with.

    Grese is a true hamdonger with this idiot action.,

    sub r15,r15,#8
    Deaf Spy what is the above instruction effect on a arm64 cpu?

    I am still waiting on an answer. I asked this properly without name calling. So DeafSpy has no arguement to avoid answering other than be a jack ass and possibly not knowing what that command is.

  40. wizard emiritus says:

    “If you did not want someone else to answer you should not have used name calling in your question to Robert.”

    I have no further words for you.

  41. Grece says:

    What’s wrong with your name HamDong?

  42. oiaohm says:

    Grece HamDong find the history. Sorry again not oiaohm that one is a stage name of a person who works in the adult video industry.

    Funny right. No so much there is a reason why name calling is taught not to be used. Its so easy to overlap with some else assigned name.

  43. oiaohm says:

    Besides wizard emiritus your question is nothing more than attempted entrapment as well. Deafspy over stepped the mark did something that owner of site cannot allow anyone to-do. This was some how defending me. Really you should be backing Robert. You have not answered why Robert should even bother answering a crap question like yours. I would not be surprised if he never answers it because a student student with anti-bulling training would know what you guys are doing is wrong and is setting a very poor example for someone who is so call mature.

    sub r15,r15,#8
    Deaf Spy what is the above instruction effect on a arm64 cpu?

    I am still waiting on an answer. I asked this properly without name calling. So DeafSpy has no arguement to avoid answering other than be a jack ass and possibly not knowing what that command is.

  44. Grece says:

    HamDong is really hyperactive, he must be tripping balls from all the medications he is taking. Maybe he will do us all a favor and OD.

  45. oiaohm says:

    The reality is that you have chosen to provide an answer a question that was directed at Robert Pogson. It was not directed at you and as a result any of the words that you directed in my direction mean nothing to me.

    If you did not want someone else to answer you should not have used name calling in your question to Robert. Not using name calling is something you should have learn in school.

    wizard emiritus think why should Robert bother answering a person who cannot understand that name calling is not on and attempt to justify it.

    Before Robert answered he need the background on the names you were using. I guess you were not aware of their history. You have a chance to wake up and pull your complaint and tell Deaf Spy to pull his head in.

    sub r15,r15,#8
    Deaf Spy what is the above instruction effect on a arm64 cpu?

    I am still waiting on an answer. I asked this properly without name calling. So DeafSpy has no arguement to avoid answering other than be a jack ass and possibly not knowing what that command is.

  46. wizard emiritus says:

    The reality is that you have chosen to provide an answer a question that was directed at Robert Pogson. It was not directed at you and as a result any of the words that you directed in my direction mean nothing to me.

    When Robert Pogson himself chooses to answer my question, I shall respond to him.

    I am through responding to you on this subject.

  47. oiaohm says:

    sub r15,r15,#8
    Deaf Spy what is the above instruction effect on a arm64 cpu?

    I am still waiting on an answer.

  48. oiaohm says:

    wizard emiritus the reality is if you are not the guilty party you are still adding the one who did it to get away by recycling handles using in such abusive actions.

    So if you keep on using the wrong handles:
    1) you are that homophobic idiot
    2) you are willing to hide what that homophobic idiot did so aid them.

    Either way I should hate you guts. This might totally explain why I was not willing to play fair and above board. Why should I play fair with total scum like you wizard emiritus. Maybe you were not aware you were being total scum coping the TMR name calling.

  49. wizard emiritus says:

    “Why I should not believe you were that homophobic idiot ”

    Why should I care?

  50. wizard emiritus says:

    “wizard emiritus I am not”

    and you prove this how? More Noise.

  51. oiaohm says:

    wizard emiritus if you keep on attempt to link to handles that are not mine. Tell me why I should not believe you were that homophobic idiot who attack that guy on youtube who is just trying to associate the handle with someone else.

  52. oiaohm says:

    wizard emiritus the reality is these people calling me these names did not invent them but used them without understand what historic acts they are linked to.

  53. oiaohm says:

    wizard emiritus I am not
    Unfortunately for you Fifi (or Ll’ Hammie if you prefer) I know that you are lying through you teeth on this statement.
    Fifi traces back to something TMR guys backed where a person was attacked for being gay on youtube who supported open source. One of DrLoser prior names on TMR took credit for it.

  54. wizard emiritus says:

    “wizard emiritus I will correct for you if you have not worked it out the real owner to handle Fifi, ohioham. lil’Hammie, the Hamster is none other than insulting DrLoser.”

    Unfortunately for you Fifi (or Ll’ Hammie if you prefer) I know that you are lying through you teeth on this statement.

    The rest of your post is noise.

  55. oiaohm says:

    wizard emiritus I will correct for you if you have not worked it out the real owner to handle Fifi, ohioham. lil’Hammie, the Hamster is none other than insulting DrLoser.

    Of course when DrLoser get sick of that handle he will attempt to palm that one off on to someone else as well. So the real owner is here. Its never been me. So what should I be answering someone else handle.

  56. oiaohm says:

    wizard emiritus fifi is one of the last ones they added to the list. So nothing like being a idiot and falling for TMR funded tricks. Wait it was you who use to use Fifi right oldman for sexual insults from TMR????

  57. oiaohm says:

    wizard emiritus
    As far as tha name Fifi is concerned, you have earned that name, along with all of the other variations on your nym (ohioham. lil’Hammie, the Hamster) that have been bestowed on you by those you have attempted to win your points over the years with lies and insults.
    Sorry all those handles predate me. So they are not my handles. So you are linking me with people who are not me. Never have been me. Just you guys are idiots on this point. ohioham was not in fact based of oiaohm.

    So the reality is those are not variations of my nym. So I should not respond to them. Basically you have believed a lie by DrLoser. Those names are all handles used by different TMR idiots who want to hide what they did by associating it with me..

  58. wizard emiritus says:

    “wizard emiritus have you forgot Robert has told everyone before that you are not meant to modify other peoples handles. ”

    Robert Pogson can refresh my memory on this by responding or providing the quote. Your input Fifi is irrelevant.

    “All I am doing is obeying Roberts rules it is his forum. Its about time wizard emiritus and Deaf Spy learn to play by them.”

    My question was directed at Robert Pogson not you. I do not care about your interpretations of those rules.

    As far as tha name Fifi is concerned, you have earned that name, along with all of the other variations on your nym (ohioham. lil’Hammie, the Hamster) that have been bestowed on you by those you have attempted to win your points over the years with lies and insults.

  59. oiaohm says:

    I don’t pretend to make the rules here, Robert. In this particular case, I assume the right to ignore Fifi until he finally answers a few simple questions, instead of vomiting incoherent texts and asking stupidities in turn.
    Deaf Spy I am in my right to ingore any one attempting to ask me a question who does not use my handle. I have used you handle and you have refused to answer.

    sub r15,r15,#8
    Deaf Spy what is the above instruction effect on a arm64 cpu?

    So answer it.

    wizard emiritus have you forgot Robert has told everyone before that you are not meant to modify other peoples handles. So ignoring Deaf Spy request when they are not to my handle is obeying the rules Robert put down. All I am doing is obeying Roberts rules it is his forum. Its about time wizard emiritus and Deaf Spy learn to play by them.

    So Robert is not defending me. Robert is up holding the rules he set down.

  60. Deaf Spy says:

    Get your own blog if you want to make up the rules.

    I don’t pretend to make the rules here, Robert. In this particular case, I assume the right to ignore Fifi until he finally answers a few simple questions, instead of vomiting incoherent texts and asking stupidities in turn.

    Gosh, I can’t believe I had to explain this to you.

  61. wizard emiritus says:

    “Get your own blog if you want to make up the rules.”

    So you are defending the technical idiot Fifi, eh Robert Pogson?

  62. oiaohm says:

    Deaf Spy sorry if a person cannot ask questions of you have no right to ask questions because a clarification question may be required. I asked a clarification of skill level question that you have not answered.

    sub r15,r15,#8
    Deaf Spy what is the above instruction effect on a arm64 cpu?

    So answer question. Robert most likely can see that this is a perfectly valid question to ask before attempting to answer you bull crap.

  63. Deaf Spy wrote, “Only then you will be entitled to ask any questions.”

    Get your own blog if you want to make up the rules.

  64. Deaf Spy says:

    Fifi, please focus on simpler stuff like Pascal’s writeln. You still have to prove you understand how this works. Then, you need to prove you understand the difference between CPU OoOE and compile-time optimizations.

    Only then you will be entitled to ask any questions.

  65. oiaohm says:

    sub r15,r15,#8
    Deaf Spy what is the above instruction effect on a arm64 cpu?

    When are you going to answer this question???

    Come on you like asking question DeafSpy???? Its a simple question. If you don’t know what that command has does there is no point explain more what was wrong with you example. The fact your stuff did not use the right label showed you had not read the cpu manual.

  66. Deaf Spy says:

    You go first, Fifi, don’t be shy. Don’t keep your vast knowledge to yourself. Bwa-ha-ha-ha-ha!

  67. oiaohm says:

    Deaf Spy really funny insulting because you don’t get. If you cannot do asm as per the manual for the CPU chip its not my problem. Its just that you are a idiot. Really here is a fun fact the first version of arm asm does not include a b statement.

    sub r15,r15,#8
    Deaf Spy what is the above instruction effect on a arm64 cpu?

    When are you going to answer this question???

  68. Deaf Spy says:

    Fifi:

    Blah-blah-blah, yackety-smackety…

    Might be perfectly legal asm for some complier but its not legal for arm made assembler or as per arm manuals

    This is a notable piece of utter non-sense. Hey, Robert, does that make you feel proud? 🙂

    Roses are read,
    Violets are blue,
    We love the sun most,
    And Fifi works under a lamppost.

  69. oiaohm says:

    Deaf Spy really no that not legal asm as per arm manuals themselves.
    http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0473f/CEGHJDFB.html
    Deaf Spy reality is google random crap really proved you were a idiot. A true arm assembler made by arm does not take : after labels.

    Really you have to be careful something like gcc with mix intel and arm syntax and at&t for good measure. The example you brought in to say you are right is a mixed breed of standards.
    Here is a perfectly legal code I just copied for you from the Internet
    Might be perfectly legal asm for some complier but its not legal for arm made assembler or as per arm manuals. So its not standard complier dependent code.

    If writing a question you should know the manual.

    Fifi, do you even know why the instructions for jumping in ARM ASM start with “b”?
    I am not fifi get it this is not asking me a question. Basically Fifi does not exist to ask questions of.

    sub r15,r15,#8
    Deaf Spy what is the above instruction effect on a arm64 cpu?

    I did ask you this question DeafSpy that you have not answered.

    Sorry you are just proving you googled up a question and did not in fact read the arm manuals to write you question correctly. Also you have not stated what that mess of code is to be built by. A good question about asm always includes what it is.

    Gcc asm for arm is not pure arm asm. Being aware what is exact can be important its like Gcc you can do a mix of intel, at&t and arm syntax in one asm segment and it build. Not like you normally present questions like that.

    arm base asm.<< refers to as per exactly the arm manuals.

  70. Deaf Spy says:

    Arm asm does not include : after labels.

    Bwaha-ha-ha-ha!

    You are amazing, Fifiest Fifi ever. How do you come up with such stupidities? Of course it does, Fifi. Here is a perfectly legal code I just copied for you from the Internet:

    @ ABS Func.
    asm_abs:
    mov r2, #1
    mov r2, r2, lsl#31
    orr r2, r2, r0
    cmp r2, r0
    bne asm_abs_ret
    sub r0, r0, r0, lsl#1
    asm_abs_ret:
    mov pc, lr

    Fifi, do you even know why the instructions for jumping in ARM ASM start with "b"?

    You don't know how Pascal write(ln) works. You don't know the difference between OoOE and compiler optimizations. You don't know anything, but standing under your lamppost, Fifi.

  71. oiaohm says:

    Deaf Spy I asked you a question as well you did not answer it. Arm asm does not include : after labels.

    Deaf Spy by the way tell the the reason why your asm will not build.
    So if someone gives you more complex arm asm in answer you don’t stand a clue of you cannot get basics right.

    By the way I am not fifi if you want to ask me something. So you have never asked me to answer you anything.

    sub r15,r15,#8
    Deaf Spy what is the above instruction effect on a arm64 cpu? This should also show a problem why rewriting intel logic question into a cpu with fixed instructing width is invalid and pointless. Its just shows that you an idiot. You were also not smart enough to change everything to the correct asm standard.

    Note Deaf Spy I have asked you a direct question using you handle you have no weaseling out room here.

  72. Deaf Spy says:

    Of course you won’t answer, Fifi. You are absolutely clueless.

    Hey, Robert, would you care to help this little friend of yours?

  73. oiaohm says:

    DrLoser
    void something() {}
    Under C and C++ standards the above has no sequence points. So the statement that functions are sequence point is a trap. Function needs arguments or a return value to have a sequence point C++ and under C arguments give you a for sure sequence point.

    Something interesting right that large function in the visual studio example has no function related sequence points because it took no arguments and provided no return value.

    + operations don’t promise sequence point.

    So in a
    a=v1+v2;
    b=a+v3;
    This code contains nothing that gives an absolute sequence point.

    At the end of an initializer; for example, after the evaluation of 5 in the declaration int a = 5;
    Many think that due to this
    int a=v1+v2;
    int b=a+v3;
    has magically fixed it but the sequence point in C and C++ don’t prevent reordering. All they mean is at at the sequence point the value better be correct. So complier rewriting
    int b=v1+v2+v3;
    int a=b-v3;
    Is valid match to the sequence points in the prior code. Since at the end of int b in both cases b equals the same value and at the end of int a in both cases they equal the same value. C and C++ give you pr0mise of value at sequence point in most case of course a few cases of not like when you are dealing with a clock value. The standard does not include an absolute order promise to get there.

  74. oiaohm says:

    Yes, of course, in the simplest way possible. Put the write and the read inside a function. Function calls are sequence points.
    DrLoser you should know better than to use my cites by now particularly pays to make sure to understand the terms they used.

    https://en.wikipedia.org/wiki/Sequence_point
    Function calls are sequence points.
    DrLoser if you had read the wikipedia or understood the standard on sequence points you would have found out that a function in C is not sequence point. By C++ standard the return functionality of a function is the sequence point. C standard function is only suggested to have a sequence point on function return not that you have to. So if something is a C complier a function might or might not have a sequence point.

    There is a sequence point at the start of a function that makes sure all the arguments for a function are ready. Neither of the sequence points in a functions mandate order functions will run in.

    In the clock(); with Visual Studio complier example it is a ; between all the function calls not a , yes ; is not sequence point so the complier is free todo what ever it like to your order as long as it does not break input/output rules. So the ; is not any different to the + example in the cite you pointed to drloser.

    Put the write and the read inside a function.
    This here that you overlooked this is so that input/output dynamics are obeyed that is 1 function as per §1.9/8. If you have two functions that are two independent sequence point and they don’t have something like a , between all bets are off. Person is in trouble because they are using two functions.

    Clock the read and write are wrapped by a function. So clock function it self is not a item identified at a input/output item and it sequence point is it return. If the function return value is not use in the next function can be reordered because is return value is not a input into function is moved past.

    DrLoser I see you problem you don’t understand the standard. The wikipedia nicely has all the cites into the standard. You could have save use form this garbage post based on incorrect information if you had checked what you had found against the wikipedia.

    As soon as person says a function is a sequence point about C and C++ straight up shows they don’t understand that a C/C++ function has 1 or 2 sequence points depending on the standard conformance and that sequence points don’t absolutely say they will be 100 percent executed in order. All they say at that sequence point everything will be in alignment for what is required.

    DrLoser does not understand C or C++ standard. Thank you for being your normal idiot and attempting to use my cites without understanding anything. The answer to the gcc cite I gave the person got wrong thank you for prove past a any question that you don’t know what you are talking about on this topic.

  75. DrLoser says:

    Oh well. The Lady Fifi insists, and I cannot deny the Lady Fifi an answer. I’ll just let my August vacation slip a bit. Does my slip show, as Fifi would say in her high-pitched, coquettish, voice?

    That drivel you came up with about “reordering function calls,” Fifi? Rather sadly, you didn’t mention sequence points. (Which are in fact the most important part of the C language standard when it comes to this particular issue.)

    No, instead, you came up with a cite which even the author admits is “contrived.” And, interestingly, you didn’t even follow the mailing list chain! How do I know this? Because the second item in that chain called out “sequence points” and explained the issue. To quote:

    A comma is a sequence point, so this part works … [code omitted for brevity. Follow the link.]

    On the other hand, the == operator isn’t, so this part doesn’t work.

    Now, you may ask yourself, is there any way to force a consistent order of function calls?

    Yes, of course, in the simplest way possible. Put the write and the read inside a function. Function calls are sequence points.

    Are you listening, you transvestite desert moron? I shall repeat:

    Function calls are sequence points.

  76. oiaohm says:

    Deaf Spy by the way tell the the reason why your asm will not build. You have a typo in your code something that you don’t do in arm asm code. If you cannot write the code right don’t ask the question in the first place. You have done something x86 that does not apply to arm base asm.

  77. oiaohm says:

    Deaf Spy sorry I made it clear long time ago I was not putting up with fifi crap. So far you have not provided a single cite prove your made up idea that I was mixing stuff up.

    Don’t you get distracted, little one. I want no more crap from you until you figure this out. It should be trivial if you possess the knowledge you claim you do.
    Still you have not used my handle. So you have not asked me for anything.

    Before I will answer anything you better be presenting cites or less. You have been told you asked fifi. You don’t have right to ask. Also robert has no reason to answer either.

    I will not answer you out of principle. I have provide cites you have not provide cites. You are now attempt to go off topic.

    You still can’t get out of the mess you got yourself into with confusing OoOE and compiler optimizations.
    Deaf Spy basically where are your cites on this. I guess you have none because you are a incompetent idiot who does not know the history of how that came into formation.

  78. Deaf Spy says:

    Don’t you get distracted, little one. I want no more crap from you until you figure this out. It should be trivial if you possess the knowledge you claim you do.


    B label;
    MOV R0, 1

    label:

    Now, the MOV instruction will get executed. Why?

    P.S. Not that I expect you to answer, or Robert. You both failed to recognize branch prediction in action once upon a time. 🙂

  79. oiaohm says:

    Deaf Spy by the way next since have put up cites. About time you put some some cites where I am wrong. Basically put up or shut up time.

    If I am wrong you should be able to prove it. Those with writeln did put up cites and I put up cites where my misunderstand come from. There was a pascal complier using the exact method I was describing. So I knew how pascal writeln worked in 1 complier but that was not the common one. Those disagreeing with me back then could put up cites. Besides asking me to answer a question means in my eyes you don’t have any references backing your point of view Deaf Spy so are a lieing idiot.

  80. oiaohm says:

    Deaf Spy forgot the rule you have no right to ask anything of me in this discussion because you are calling me fifi.
    Now, the MOV instruction will get executed. How is this called?
    Next time think about using a person proper handle then you can ask them questions. You called me fifi you must have believed you did not need to ask me a question. So to late to change now. Don’t bother asking another question this thread. You shot yourself in foot.

    You still can’t get out of the mess you got yourself into with confusing OoOE and compiler optimizations.
    Out of Order Execution in cpu is based off of complier optimizations for in-order cpus. Out of Order Execution is mostly to allow code poorly optimized for current cpu to perform more effectively.

    Only a person who is a idiot who did not know the history of OoOE would say they are not interlinked.

    Complier reordering optimizations and OoOE in cpu are both based off the same basic things. Please note I have provide a two links both demo the same kind of fault one happening because of complier and one happening at random intervals due to OoOE.

    The interesting part is mulithreaded optimization first appears in OoOE in particular power cpus before again by IBM then becoming a complier optimization feature.

    So advancements in compliers have moved to OoOE and some advancements done on the OoOE side have moved to compliers. Those who don’t know the history of the features will make the stupid claim that a person is mixing up OoOE and complier optimization features when history has both side trading methods with each other.

    Deaf Spy really same clueless statements thinking that I have include the cites showing OoOE and complier pulling the same stunts.

    There is a difference complier normally processes and performs the optimizations over a larger area of the executable than OoOE but that is it for modification differences and that makes no difference number of possible outcomes. Key thing OoOE side effects with have random if this time it happens or not and complier reorder will be predictable so happen every time the code run. The fun part is OoOE can nicely mask complier reorder issue.

    The interactions between complier reording and cpu OoOE gets quite fun. This is where is cool on arm where you have a inorder cpu type to debug some complier issues and it takes exactly the same instruction set as the OoOE cpu.

  81. Deaf Spy says:

    Now, Fifi, an exercise for you.

    You say you know ARM, right? See this tiny snippet, Fifi…


    B label;
    MOV R0, 1

    label:

    Now, the MOV instruction will get executed. How is this called?

  82. Deaf Spy says:

    Twist as much as you want, Fifi. You couldn’t understand how write(ln) works and spewed a river of non-sense on the subject. I am sure you still don’t understand it. And this is something as simple as it can get.

    You still can’t get out of the mess you got yourself into with confusing OoOE and compiler optimizations.

  83. oiaohm says:

    Deaf Spy please note the strangeness of out of order execution and complier reordering comes critical when you are dealing with cpu interfaceing with hardware devices by memory addresses. At times you will have values set at the wrong time.

    http://preshing.com/20120515/memory-reordering-caught-in-the-act/
    This is OoOE is doing the same thing as Gcc and complier do in optimization stage with modified order of execution except its nicely random. Yes this example here particular prevents the complier from doing only to have the cpu reorder it anyhow.

    So the order you presume a value alteration will happen will change unless you tell the complier optimiser and if you are using OoOE cpu not to will be random.

    You confuse compiler optimizations with OoOE done by the CPU.
    I have not confused this at all the issues caused by OoOE done by CPU and complier modified order of execution can be identical. Those on Intel CPU never see multi threaded speculative OoOE you find that inside a IBM designed power cpu.

    Most of the belief that complier optimization and OoOE are very different is more never notice what the advanced complier optimizations do and what the most advanced OoOE can do. Yes the power OoOE take take a single threaded program in and spread it execution over multi cores. So your single thread program sliced up and run on multi cores might be done by the complier also might be done by the CPU OoOE with your order of events not being what you expect them to be.

    So modified order of execution and OoOE can both ruin your day.

  84. oiaohm says:

    Deaf Spy really funny.
    1) pascal is not language where I have build a complier C and C++ I have built compliers.
    2) the way I described pascal writeln working did match how one of the real world compliers did it.

    You confuse compiler optimizations with OoOE done by the CPU. You’re pathetic. Sod off, little one.
    For effects on execution of code both can be related. I have not confused.

    The reality here is the pascal writeln one you said I was wrong when I had in fact given a real pascal complier that did it that way. Ok I was not aware that it was breaching standard as far as it was.

    Deaf Spy and it not like everything you have posted has always been 100 percent correct either. This case the standard allows reordering. Real world complier do the reordering. I have done cpu in vhdl with OoOE so I do understand the effects that OoOE and complier optimization can cause.

    Reality here you are a moron who presumed I did not know this topic. It should have been a waring when a long time go I gave the C code that demoed that unallocated memory under Linux was not a random data source proof. Keep on being a idiot and presume I am clueless the reality is I am not clueless. I have got some thing wrong.

    Please note DrLoser claimed a pure lie that standard compliers don’t reorder yet you deaf spy are come after me alone. Lets just say you nicely ignore one the other liers lie at lot. Apply you standards evenly. Also it would be handy if you go back and look at that writeln one because I gave the links to the complier that did it the way I said after the last post of yours so I would presume you never read it.

  85. Deaf Spy says:

    What’s up, Fifi? Seems you had a few good nights under the lamppost, now that you have so much time to spend here and pollute this unfortunate place with your ramblings.

    But Fifi, you can’t figure out how Pascal’s writeln works, yet you dare speak of OoOE. You confuse compiler optimizations with OoOE done by the CPU. You’re pathetic. Sod off, little one.

  86. oiaohm says:

    DrLoser function reordering is in the murky area of standard undefined. The standard only defines that functions will happen in a predictable order if particular conditions are meet.

    https://developer.arm.com/docs/den0024/latest/13-memory-ordering

    Now it gets interesting when you are talking about arm.
    https://en.wikipedia.org/wiki/ARM_Cortex-A53
    A53 is a in-order processor. You cannot depend on the cpu using out of order execution. So for cache effectiveness reordering the code to run simpler code close to each other increase performance.

    Complier reordering execution order starts with how to get cache and performance effectiveness on cpu with in-order execution. So is a very old complier optimization technique. Reality this is one of the basic behaviors of a complier. Since a basic behavior of a complier you need to read program language standard carefully to understand what you have to-do to prevent it from happening.

    The biggest issue migrating x86 C to arm C is more often than not issues coming out form different reordering patterns. Yes gcc reorders different on arm and x86 even with the same complier version. Of course if you code is not coded right and this happens a new version of gcc could also trigger it to happen.

    DrLoser failure is normal people presume C and C++ standard has a order of execution promise when it very limit by §1.9/8 in the C++ standard and there is a equal in the C standard. Since the promise is limit those writing C and C++ optimizers go for it. Why your program under gcc can work fine with -O0 yet complete die with -O2/3 mostly because you have done something order dependent without tell the complier or doing in a method inside §1.9/8 requirements.

    People think pointers are the most dangerous problem of C and C++ the re-ordering is quite a dangerous little problem. Of course re-ordering and refactoring adds a new level of evil once you add in openmp and the like taking your single threaded code and converting it into multi-threaded code. So not only was you code reorder it been chopped up to run in parallel.

  87. oiaohm says:

    DrLoser
    There is no conceivable way that any standard-conformant C compiler or C++ compiler will allow “re-ordering” between two calls to a subroutine, clock() or otherwise. And every single Microsoft C or C++ compiler that you care to quote is, at least in this limited sense, standard-conformant.
    https://gcc.gnu.org/ml/gcc-help/2008-09/msg00209.html
    Reality here gcc will do it as well. Reality here the standard does not say the compliers it not allowed to. Reordering called to subroutines is in fact allowed. The volatile declare in C and C++ standards exists to prevent this from happening.

    You know I claimed that no standards-compliant compiler would allow re-ordering across two subroutine calls, oiaohm?
    Gcc and Visual C++ are both standard-compliant compilers with this behavior.

    Issue here DrLoser you are presuming the standard forbids something when it does not. I can keep on Listing C and C++ compliers that do it. It is a trap that can get you big time.

    Of course DrLoser not doing research comes out attacking like a idiot. It would not have been hard to check if any standard conforming complier does it as well the answer is yes gcc, llvm, Intels, Ibm complier for AIX…….. So fairly much every majorf C and C++ compliers reorders stuff.

    DrLoser reality for the way you describe sluts you must either like dressing up as one or are one. Kinda explains why you have not gone and read the standard references I provided and failed to check if standard conforming complier does the same thing. Reality here is Microsoft complier sometimes is to standard. I reference it first instead of gcc of llvm or other standard confirming compliers first most to see if DrLoser had had his brains ruined by STD.

  88. DrLoser says:

    Oh heck. One last chance to show oiaohm up for the useless ignorant loser he is, whilst I take a well-deserved vacation from this blog for a month.

    You know I claimed that no standards-compliant compiler would allow re-ordering across two subroutine calls, oiaohm?

    I intentionally left out the case where, in fact, a standards-compliant compiler is allowed to do this.

    Now, in the intervals between “satisfying” your “clients,” may I suggest you lie back and ponder this question? Two answers, please.

    1) When is this permissible of a standards-compliant compiler?
    2) Why does this not apply to clock()?

    Fifi, you ignorant slut.”

  89. DrLoser says:

    And for anybody who is not a miscegenation between toe fungus and organic fertiliser:

    “Speculative threading” is just that, Fifi. It is speculative. (I’ll accept the vague hand-wavy “threading,” although that is tbh another sign of devastating ignorance on the subject.)

    What is never permissible, no matter which architecture you use (short, I will confess, of Quantum Computing), and no matter which compiler you choose, is speculative pipe-line operations that involve irreversible side-effects.

    Only a moron whose sole income derives from hanging out at dusk, back of Bourke, under the only lamp-post for fifty miles, would even suspect that it could be otherwise.

    Congratulations, oiaohm. You ARE that moron.

  90. DrLoser says:

    For the record, oiaohm: no.

    There is no conceivable way that any standard-conformant C compiler or C++ compiler will allow “re-ordering” between two calls to a subroutine, clock() or otherwise. And every single Microsoft C or C++ compiler that you care to quote is, at least in this limited sense, standard-conformant.

    You are of course welcome to cite evidence where this is not so, you wretched snivelling haploid genetic splice between what a dung beetle plays around with for fun and the world’s least exciting piece of toe fungus.

  91. DrLoser says:

    This is what you guys never got with using Fifi and the like. All it will mean is I will be less likely to give you complete information.

    How may we distinguish your proposed “less likely” from your quotidien “utterly incapable,” Fifi?

    I think you might have dropped an epsilon or two, there, you fishnet-stockinged incompetent cheap slut.

  92. oiaohm says:

    Deaf Spy what an answer try using my correct name. I will tell that every one that Robert lists.

    There are many caching algorithms possible: on, off, most recent priority, most frequent priority, some processes only, private, shared, dynamic, static until the process completes…
    Are real ones you can find inside a arm64 cpu.

    “ARM Caches: Giving you enough rope… to shoot yourself in the foot”
    You really do need to look up on this talk. Process completes is slightly wrong static until ASID is disposed of to be correct. You would expect a process and ASID to be linked. “Some processes” is that the cache method in Arm64 can be set per ASID.

    Static load into cache was design for arm trusted mode. Its interesting that with trust mode action it can bipass the mmu and come from storage device straight into the cpu cache. ” static until the process completes” is one of the specialty ones I don’t know of on any other cpu other than arm.

    Deaf Spy basically Robert gave you a perfectly correct arm cpu answer. Of course leaving out minor detail of using 1 ASID per process of course being either 8 bit or 16 bit is a limit. ARM not the only cpu that has something like a ASID.

    Deaf Spy keep me laughing at how much you claim does not exist but is sitting in physical hardware in my hand.

  93. Deaf Spy says:

    Deaf Spy basically roberts answer is right

    Well, well, well. Then, Fifi, please tell us: which of the “many caching algorithms possible” (ref. Robert) does ARM architecture use? And why?

    I hope you won’t say “some processes only” or ” static until the process completes”. These two are particularly hilarious and even an idiot like you won’t say such things. Or maybe you are such an idiot, after all.

    Come of, Fifi, make us laugh again. 🙂

  94. oiaohm says:

    Deaf Spy basically I provide a real world example over that clock one because I knew you idiots would argue that it cannot happen and it cannot be to standard when it does happen and it is to standard and you guys are too big of idiot to know any different.

  95. oiaohm says:

    I am sorry, Fifi. You got it all wrong. The Doctor wrote that clock() can’t be reordered. You answer that using volatile will stop the CPU from reordering clock(). You can’t write, you can’t comprehend written text. You are really hopeless, aren’t you?
    Deaf Spy no the link was a person asking about real world event that happens with Microsoft visual studio C++ complier. Where it does in fact reorder clock(). DrLoser and you idiot might claim different but the reality with compliers it does happen. Shock horror its exactly to standard to be reordered.

  96. oiaohm says:

    Damn, the good doctor is right. Not a single sentence makes any sense whatsoever. I don’t know whether that’s progressing dementia, or alcoholism, or some other substance abuse. But one thing is clear: you have totally no idea how CPU cache works.
    LOLOLOL Deaf Spy so now you are attempt to do to robert what you do to me.

    Please learn to read.

    >>In principle, one could enable the cache or clear it for particular processes. That would require clearing for context-switches, but if everything is cached a context-switch need do nothing particular with the cache.<<

    This line here is why arm cpu don't need to clear the instruction cache.

    https://cs.stackexchange.com/questions/1088/what-happens-to-the-cache-contents-on-a-context-switch

    Context switch on x86 mandates particular things happen to the instruction cache.

    http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.den0024a/CDDEIJCH.html

    Context switch on arm64 different matter. The fun part about using something with Address Space ID (ASID) so information in the instruction cache can be tagged as owning to particular ASID. So you don't need to flush the instruction cache any more this does make arm64 processes perform better in context switching than x86.

    But one thing is clear: you have totally no idea how CPU cache works.
    Deaf Spy try again you don’t have a clue how CPU cache works outside x86. Power and arm are very different beasts particularly when it comes to context switching. Some ways the stuff like ASID is like x86 hyper-threading .

    Any cpu with something like ASID does not need to flush any of the caches on context switch change.

    Deaf Spy basically roberts answer is right and you are just an absolute narrow minded idiot. What Robert said is true there are many different ways a cpu can implement caching the way x86 does flushing is required in a lot of cases. Way arm and many different mips do is different so not as much cache flushing is required. Particularly if it short run context switch.

  97. Deaf Spy says:

    I am sorry, Fifi. You got it all wrong. The Doctor wrote that clock() can’t be reordered. You answer that using volatile will stop the CPU from reordering clock(). You can’t write, you can’t comprehend written text. You are really hopeless, aren’t you?

  98. oiaohm says:

    Deaf Spy by the way it alway good seeing a idiot like you attempt to make a point if you don’t get it its more fun doing write up point out your crap then doing other writing prac. So no matter how much you insult me its not going to make me go away. This is what you guys never got with using Fifi and the like. All it will mean is I will be less likely to give you complete information.

  99. Deaf Spy says:

    I never suggested a cache be that large, but caching all the data/instructions fetched/written by the CPU/caching the whole address-space.. In principle, one could enable the cache or clear it for particular processes. That would require clearing for context-switches, but if everything is cached a context-switch need do nothing particular with the cache. There are many caching algorithms possible: on, off, most recent priority, most frequent priority, some processes only, private, shared, dynamic, static until the process completes…

    Damn, the good doctor is right. Not a single sentence makes any sense whatsoever. I don’t know whether that’s progressing dementia, or alcoholism, or some other substance abuse. But one thing is clear: you have totally no idea how CPU cache works.

    Now I see why you’ll never buy your fabled ARM chip / motherboard – you will complain of the small cache. 🙂

  100. oiaohm says:

    Deaf Spy funny how the insults come out when you are wrong.

  101. Deaf Spy says:

    DrLoser … you have lost right to any more cites

    Fifi, you have lost all your dignity years ago. We might only have occasional laugh at you, but most of the time we simply ignore your meaningless drivel. Get back to your lamppost, Fifi.

  102. oiaohm says:

    DrLoser shock horror right that the 4 possible outcomes is what happens when you are using a C or C++ conforming complier that support multi threading with speculative threading. There are every time when gcc alters it modified order of execution you you see more sections in the Linux kernel marked volatile to prevent complier being creative and reordering stuff. Instruction reordering and rewriting is what compliers do include like changing printf for fputs for speed. Failure to allow for compliers doing this stuff is path to code surprises down the track. Failure to read the standard fully and understand what its mandated and what is not also causes the problem.

    Lot of people incorrectly presume when you code C or C++ that the order of execution and if execution is single or multi threaded is defined by standard without doing anything. Default is fairly much what ever the complier likes.

  103. oiaohm says:

    DrLoser you used fifi in a comment response to me in this thread so you have lost right to any more cites. Really I provide one real world example of instruction order modification by complier. The 4 different out comes is what happens when compliers modify instruction order for pure reasons for multi threading.

    modification of instruction order started back in 1997 in single threaded to increase cache efficiency. Multi threading can gain from instruction order modification can increase cache efficiency again due to CPU L1 caches.

    #include

    auto t0 = clock();
    auto r = veryLongComputation();
    auto t1 = clock();

    std::cout << r << " time: " << t1-t0 << endl;

    into this form:

    auto t0 = clock();
    auto t1 = clock();
    auto r = veryLongComputation();

    std::cout << r << " time: " << t1-t0 << endl;

    This modification is not a theoretical event.

    https://en.wikipedia.org/wiki/Volatile_(computer_programming)

    (cannot! As required by the C++ standards! be elided, nor reordered, by the compiler).
    DrLoser please not presume what is written in the standard.

    §1.9/8 section what is missing is a keyword.
    Access to volatile objects are evaluated strictly according to the rules of the abstract machine.

    volatile

    auto volatile
    t0 = clock();
    auto volatile
    r = veryLongComputation();
    auto volatile
    t1 = clock();

    So this code will not be reorder in major ways because you told the complier not to.

    Reality is both C and C++ standards allow a heck of a lot of complier reordering particularly if you fail to tell the complier its not allowed to. This level of reordering goes to a completely massive increase in effects once you start dealing with openmp.

    DrLoser go and read the C++ and C standards carefully. Both the outputs of the time call are not used by the code in the middle.

    Every value computation and side effect associated with a full-expression is sequenced before every value computation and side effect associated with the next full-expression to be evaluated.
    So the next expression is not using the value not not breach of §1.9/14. Lot of people incorrect read §1.9/14 forbids reordering when it does not.
    a=v1+v2
    b=a+v3

    a=v1+v2
    b=v1+v2+v2
    Both end up with the same result in values a and b and if a and b happen to be run on other threads as long as they a process before a and b are used by something else its legal. So single or multi threaded who knows by the standard unless you declare.

    This provision is sometimes called the “as-if” rule, because an implementation is free to disregard any requirement of this International Standard as long as the result is as if the requirement had been obeyed, as far as can be determined from the observable behavior of the program. For instance, an actual implementation need not evaluate part of an expression if it can deduce that its value is not used and that no side effects affecting the observable behavior of the program are produced.
    §1.9/1 this is note about what it covers so it allows a lot of modification.

    The least requirements on a conforming implementation are:

    — Access to volatile objects are evaluated strictly according to the rules of the abstract machine.

    — At program termination, all data written into files shall be identical to one of the possible results that execution of the program according to the abstract semantics would have produced.

    — The input and output dynamics of interactive devices shall take place in such a fashion that prompting output is actually delivered before a program waits for input. What constitutes an interactive device is implementation-defined.

    §1.9/8 puts limitations of what you have to care about when writing a C++ complier. Are the clock reads in the same order after being moved answer is yes so input/output is right. Was anything in the first example marked volatile the answer is no. Did the order change effect when the program terminated no. So was a valid reorder by C++ standards. You find the same thing in C standards.

    Failing that — and I promise you, you will fail — we’d all love to see a cite describing how you “contributed” to mingw. Did they have a hanky that needed to be filled with snot or something?
    Sorry you have lost the right to ask for that DrLoser. I have been clear in a thread you use fifi you lose right to ask for anything of me.

  104. Grece says:

    I concur, a check-up from the neck-up, is in need.

  105. DrLoser says:

    Oh, and Robert?

    You do, seriously, need to get yourself checked up by your doctor. I’m serious about this. You are definitely exhibiting signs of dementia. You’re even more crotchety than you normally are, and you’re periodically drifting off into whole swathes of nonsense. You weren’t doing this a couple of years ago.

    Check with TLW, please, and if “She Who Must Be Obeyed” — a Rumpole reference, as you would have known before your memory caved in — agrees with me, I think it’s time for a check-up.

    Oh well, off for the traditional Vacances d’Aout.

  106. DrLoser says:

    Code that attempts to disallows parallel instruction execution will result in a few different outcomes when it hits a complier.

    Here’s an interesting test, oiaohm. You have made this “extraordinary” claim. Now, in the general run of things, you would need to offer up “extraordinary” proof.

    But not in this case, you fatuous moron. In this case, all you have to do is to offer up some sample code “that attempts to disallows parallel instruction execution.”

    Do feel free to astonish us, oiaohm.

    Failing that — and I promise you, you will fail — we’d all love to see a cite describing how you “contributed” to mingw. Did they have a hanky that needed to be filled with snot or something?

  107. DrLoser says:

    And to be absolutely fair.

    Fifi, this is not a race to the bottom. (Although that may well be a game you play under the lamp-post late on a Friday night.)

    You are welcome to tell Robert that he is being an ignorant fool. In the same way that Robert is welcome to tell you that you are being an ignorant fool.

    But don’t, please, let me interfere. Both of you mental cripples appear to have a desperate deed for each other.

  108. DrLoser says:

    I never suggested a cache be that large, but caching all the data/instructions fetched/written by the CPU/caching the whole address-space.. In principle, one could enable the cache or clear it for particular processes. That would require clearing for context-switches, but if everything is cached a context-switch need do nothing particular with the cache. There are many caching algorithms possible: on, off, most recent priority, most frequent priority, some processes only, private, shared, dynamic, static until the process completes…

    Quoted in its entirety, for the full, awesome, effect.

    Not a single sentence of that makes any sense, Pogson, you abject fool. Not a single clause!

    Ignoring the fact that you did, originally, suggest that a computer can use the entirety of RAM as cache … you are presently demonstrating a compete inability to understand what “CPU cache” means. Congratulations! This is even more moronic than Fifi’s inability to follow the logic of her own cite, and figure out that clock() has side-effects that cannot (cannot! As required by the C++ standards! be elided, nor reordered, by the compiler).

    That entire paragraph was hopeless senile drivel, Robert. You seriously need to see a doctor, right now.

  109. Deaf Spy wrote, “Explain the funny case when the cache will be large enough to fit the entire RAM”

    I never suggested a cache be that large, but caching all the data/instructions fetched/written by the CPU/caching the whole address-space.. In principle, one could enable the cache or clear it for particular processes. That would require clearing for context-switches, but if everything is cached a context-switch need do nothing particular with the cache. There are many caching algorithms possible: on, off, most recent priority, most frequent priority, some processes only, private, shared, dynamic, static until the process completes…

  110. Deaf Spy says:

    Totally irrelevant to Robert’s issue, Fifi. As usual.

    Robert, don’t let the poor maroon distract you. Explain the funny case when the cache will be large enough to fit the entire RAM. And don’t forget to find us a modern CPU + MB that has it. 🙂

  111. oiaohm says:

    And since when OoOE is compiler’s job, Fifi?
    Deaf Spy its not called OoOE in a complier. It has two names in a complier called modified order of execution. its a optimization in complier stunt.
    https://stackoverflow.com/questions/26190364/is-it-legal-for-a-c-optimizer-to-reorder-calls-to-clock
    You see people complain when it happens to cause a different result like in this stackoverflow and you will find issues with modified execution order done by compliers going back to 1997 so 20 years ago it appeared just restricted to single threaded. Modified order of execution is the complier right to rewrite your code to what it thinks is more effective. So a = b + c, d = a + e rewritten by complier a=b+c, d=b+c+e is perfectly correct.

    You see optimizer do more massive rewrites like a=v1*1000+v2*100+v3*10+v4 rewritten by complier to or from a=((v1*10)+v2)*10+v3)*10+ v4. All complier in modified execution attempts to care about is that the result will be the same. Not always true when value comes from dynamic sources like real-time clock so you need to tell the complier not mess with those things.

    This is like first generation out of order execution in CPU except done by complier as modified order of execution. Complier modified order of execution caused bugs can cause some really creative bugs to track down.

    https://www.ibm.com/support/knowledgecenter/en/SS2LWA_12.1.0/com.ibm.xlcpp121.bg.doc/proguide/bg_se_concept.html
    Until IBM did this speculative execution was not in the complier and only part of cpu out of order execution. This is current day you building your code with openmp with speculative on a lot of things that you would think cannot be in parallel execution turn out to be.

    So I included IBM link of when Modern day Out of order execution in cpu came the same as modified order execution in complier for the ruining how predictable if something is parallel or not..

    There is one big difference between modified order of execution and out of order execution in cpu. Modified order of execution is written into the program machine code so does not change every time the program runs from the same binary.

    Yes out of order execution by cpu and modified order of execution by complier at times can create some really interesting bugs partially like the get the clock real-time clock before and after a long task and getting the result 0. Only way that happens is the code was reordered. When you add in openmp and breaking the code into threads automatically and being speculative a lot of bets are off.

    Code that attempts to disallows parallel instruction execution will result in a few different outcomes when it hits a complier.
    1) the complier rewrites so it does in fact run in parallel quite well.
    2) the complier rewrites it and uses speculative so is wasteful on cpu resources.
    3) the complier rewrites it and magically creates strange new bug were data appears to be time traveling.
    4) it happens to be successful at disallowing parallel execution and this might be because you were smart enough to tell the complier not to.

    Out of this least problems is if either 1 or 4 happen. 2 could be bad performance or performance boost. 3 real complete nightmare because you can go over the source code all you like and it looks perfect as it the complier generating the binary ruining your day.

  112. Deaf Spy says:

    No Deaf Spy you are not aware how compliers or cpu optimize stuff

    And since when OoOE is compiler’s job, Fifi?

    I worked on the mingw project and a few other complier projects submit fixes.

    You’ve worked only under the lamppost in your hometown, you fishnet-stocking bearer.

    You are fraud, Fifi, a fraud and self-admitted liar.

  113. oiaohm says:

    Deaf Spy out of order optimization can be done by the complier as well. You will see this out of openmp enabled gcc as well.

    Fascinating, Fifi. Honestly, I am speechless.

    Robert, do you still insist that Fifi is technically knowledgeable?
    No Deaf Spy you are not aware how compliers or cpu optimize stuff. Its a lot harder to be sure your code will not be multi threaded. Particularly with the introduction of performance based cpu time wasting when threading. So you spin up a threads that you may never use the result of to reduce response latency.

    DeafSpy I worked on the mingw project and a few other complier projects submit fixes. So I worked with how compliers transform what you feed into them and what in fact end up going to the cpu and what the cpu end up doing to your code.

    Or code that disallows parallel instruction execution (a = b + c, d = a + e).
    Basically you put this example up against a complier using like openmp well and it will rewrite it every single time. a=b+c and d=b+c+e because sending to multi threads and doing a few extra additions is nothing to worry about.

    Cpu out of order execution and complier modified ordering of execution really starts messing with all the ideas of what is disallows parallel instruction execution.

    https://www.ibm.com/support/knowledgecenter/en/SS2LWA_12.1.0/com.ibm.xlcpp121.bg.doc/proguide/bg_se_concept.html
    The section of complier and cpu out of order execution messing with stuff is when you get into the fun world of https://en.wikipedia.org/wiki/Speculative_execution Speculative execution. So stuff magically runs parallel instruction execution the question is at what CPU time waste percentage to allow for wrong guesses.

    Deaf Spy basically you were correct 20 years ago. Modern compliers and cpu you example was not complex enough. Even locking examples can be in fact running in parallel instruction execution due to speculative execution by cpu or complier.

    It gets very hard on modern day compliers and cpus to be sure your code is not running in parallel without particularly doing things to enforce this.

    Deaf Spy basically this case you are out of date not up on what asm end up at the cpu and what the cpu does to it after that. Old compliers your code was not going to end up multi threaded modern compliers do you fell lucky.

    kurkosdr
    Don’t you think it is embarrassing that me, an ESL speaker has to correct you, a native speaker, so many times? Do you plan on doing anything to remedy that deficiency of yours?
    kurkosdr if you were getting your corrections correct it would be embarrassing. Really over and over again you show that you are ESL speaker like the by addition that is a non native mistake. Same with not being aware that writing as a word has plural and single context.

    The fact you are not native and you pretend to know english means I should write to you in only ways native english speakers would understand. Of course every time I do you don’t get a thing. Reality you don’t get your deficiency so until you do you stand no chance of correcting my english correctly or reading some of my insults to you.

  114. kurkosdr says:

    This is you adding things to make your mind fill better. Doing stuff is used because it is possible for you to get it right if you are really careful. But you track record of doing alterations.

    Ok, whatever. I didn’t quite get what you were trying to say with “doing stuff” (please be more vague…). How about all the other “formal English” stuff I had to correct?

    Don’t you think it is embarrassing that me, an ESL speaker has to correct you, a native speaker, so many times? Do you plan on doing anything to remedy that deficiency of yours?

    Nothing is more embarrassing than having a CV which lists “English” as your native language and you speaking that language so badly to the point of being incomprehensible (at times). And writing in a similar way.

  115. Deaf Spy says:

    a=b+c, d=a+c comes a=b+c d=b+c+c after cpu out of order execution has played with it it can also come warped as a=d-c with d=b+c +c.

    Fascinating, Fifi. Honestly, I am speechless.

    Robert, do you still insist that Fifi is technically knowledgeable?

  116. oiaohm says:

    So you have just accuse[d] me of something I don’t do in my writing[s]. If you are attempt[ing] to correct my stuff [by] doing [correcting?] stuff [mistakes?] I never do, of course you are going to be getting it wrong.

    Lo and behold gentlemen, “formal English”

    Sorry go open up world book attempt and accuse are used that way particularly. Writing and writings is interesting because writing is a plural and a single where writings is a plural. So the non s version of writing that context is more correct.

    [by] doing [correcting?] stuff [mistakes?] This is you adding things to make your mind fill better. Doing stuff is used because it is possible for you to get it right if you are really careful. But you track record of doing alterations.

    my stuff [by] doing [correcting?] stuff [mistakes?] I never << I would say read this out loud and notice that "stuff by doing" Stalls worse on the tough than "my stuff doing stuff." Fail the read test mean it a invalid add. This is a mistake computer grammar checkers make but those trained in english should not make.

    https://www.languagetool.org/

    If you are attempt to correct my stuff doing stuff I never do of course you are going to be getting it wrong.
    In this line there is only 1 require correction. In fact is the first word should be removed being “If”. Other wise the complete line is correct. This is more often the case not missing a word 1 or 2 extra.

    Now of course “writing stand” me using short hand for writing standard yes telling me off of this would be fine. Please note have not increased number of words. Every time you have increase number of word you get it wrong. Simplified Legal English you get away with it because http://www.macmillandictionary.com/dictionary/british/stand_1#stand_1__38 of the meaning 8 here of stand.

    Kurkosdr the reality here I am writing to bare min Simplified Legal English. Please note min are long form of Simplified Legal English that has to be minimum and use of stand instead of standard would not be permitted either in long form.

    Read this out to any normal person and observe how they will respond, I dare you.
    I have read that out to many normal people of course only correction is using standard instead of stand. I will give that short hand was a error. Normally they ask is what I write to any particular standard and the answer is yes it is and normally after they have seen the 8+ standard I have to write to with the conflicts they go it makes sense to go to bare minimum.

    Kurkosdr of course you still have not said what writing standard you are using. I am using one and I would guess you are not. You still love doing totally not valid corrections.

  117. Kurkosdr says:

    There is a reason why a lot of my formating is missing is that depend on what writing stand a document I write is for depends what punctuation added in the proofing stages.

    Read this out to any normal person and observe how they will respond, I dare you.

    So you have just accuse me of something I don’t do in my writing. If you are attempt to correct my stuff doing stuff I never do of course you are going to be getting it wrong.

    So you have just accuse[d] me of something I don’t do in my writing[s]. If you are attempt[ing] to correct my stuff [by] doing [correcting?] stuff [mistakes?] I never do, of course you are going to be getting it wrong.

    Lo and behold gentlemen, “formal English”

  118. oiaohm says:

    Kurkosdr open up and read the world book encyclopedia some time. You will notice something interesting. No such thing as a single comma used in the complete text. The base punctuation I use is world book encyclopedia standard and it also a standard used by many journals. Objective to to keep text as compact as possible in printing and not to expand the text with optional punctuation marks.

    -Punctuation marks aren’t to be omitted, they define the “code blocks” of the language, and when you “imply” punctuation marks you throw the reader out of sync and the reader has to do a double-take, and even then he MIGHT understand what you are saying.
    Basically complete crap. I am using Punctuation to a very particular english standard. I can give a long list of books you can go to in a library to open and find the standard. So are all those books wrong. I think not. Its you who are wrong.

    -Context of a quote doesn’t act as a sort of “parent class” that allows sentences to inherit words like the word “valid” you omitted in the “no valid market” phrase.

    This is a miss belief there is no require in a Context response to copy any more than the base number of keywords words. No and Market were all that was required. Use of valid using world book encyclopedia style guide is excessive word.

    Kurkosdr reality here you think your english is good when you don’t know enough to make a valid arguement.

    The way I use punctuation is in fact in a formal style guide.

    Who am I kidding? You can’t. Start from the basics like SVOMPT and quoting phrases properly (without removing keywords) and move from there.
    Was valid a keyword in no valid market. No its not a keyword. So when you understand what a keyword means comment again.

    https://en.wikipedia.org/wiki/Keyword_(rhetoric)
    Reality no matter what form of keyword logic you use it was not keyword. This is why I did not copy it. Now can a market exist if it not valid the answer is no. So a market if talking about a real thing has to be existing so valid in “no valid market” is an optional emphases word. Now you could have complained about me removing excessive emphases and that would have been correct. Complaining about keyword totally incorrect. Key feature of a proper keyword is the fact you cannot remove it without altering meaning. So here is you again complain about something that is totally optional by the rules of english.

    My usage of no market was not a quote it was a response so not require to quote exactly. Basically stop asking me to do stuff rules of english writing don’t require.

    layman English us normal people use. it was layman English 40 years ago. Its is a english standard that is still used. The reality just because I am writing in a different standard than you what gives you the right to attempt to tell me to change. I could nit pick what you are writing and point in you last post to 100+ errors to 8 different style guides all defined as layman styles. Best part the conflict with each other. There is no such thing as a layman English style only people who tell a person who write layman are a idiot because it cannot be done. Each region has it own define of layman English.

    Shock horror most of what I write passes Simplified Legal English punctuation style as well including not having that colon and leaving out word valid in the case you picked on.

    So far you have not said what standard you are comparing my writing to and layman is not an answer. I bet it a stack of collected garbage you have collected over you years.

    Formal english means you are obeying a style guide not winging things.

    Simplified Legal English is one of the standard officially marked as layman english. So before complaining about english please tell everyone what standard are you using or don’t you know.

  119. Kurkosdr says:

    Really?

    Look, moron, people may “understand” you, in the same way they “understand” a toddler talk, but everybody agrees on the fact your English are terrible.

    Let me give you some hints:

    -Punctuation marks aren’t to be omitted, they define the “code blocks” of the language, and when you “imply” punctuation marks you throw the reader out of sync and the reader has to do a double-take, and even then he MIGHT understand what you are saying.

    -Context of a quote doesn’t act as a sort of “parent class” that allows sentences to inherit words like the word “valid” you omitted in the “no valid market” phrase.

    Look, if you want to believe that the toddler-speak/Yoda-speak combo that you speak is “formal English”, keep believing that (I suppose I cannot convince you it’s not), but if you want to be taken seriously in life, please use the layman English us normal people use.

    I suppose you can do that?

    Who am I kidding? You can’t. Start from the basics like SVOMPT and quoting phrases properly (without removing keywords) and move from there.

  120. oiaohm says:

    Yeah, I guess anybody could figure out that a colon is missing.

    kurkosdr colon there is classed as bad style. You get into trouble doing it in newspapers.

    Nobody is in your head (fortunately if I might say) and nobody else shares your weird syntax rules (OhioLang™) or your weird opinions about what should be guessed when reading stuff and what not.
    If you go and look up the formal usage of colon you will find the usage there is option and strictly forbid in particular types of writing. So anyone who is properly trained in english should have been presuming possible missing : before looking at comma.

    People aren’t supposed to guess missing words
    kurkosdr this is where you completely read my stuff wrong all the time. I am never missing words. I have sometimes typed the wrong word. Basically every time you have told me that you have added a word. I have shown you that it was in fact correct without it and it was a error to add it in the first place. You should have worked out by now I don’t miss words. At worst I typo a word.

    So you have just accuse me of something I don’t do in my writing. If you are attempt to correct my stuff doing stuff I never do of course you are going to be getting it wrong.

    In fact I am more likely to double type a section than been missing a word.

    I suggest you drop the idiotic “everybody speaks English wrong except me” attitude and learn how to produce valid sentences in English.

    I wish you would stop pulling out the perfect valid sentences. There are sentences with issues that you fail to find.

    The colon one by all common academic writing standards is if you include it after the person name is invalid and is meant to be presumed. In casual writing it optional. So what was missing was exactly what you should have been presuming was included before changing anything.

    There is a reason why a lot of my formating is missing is that depend on what writing stand a document I write is for depends what punctuation added in the proofing stages. Of course you have never had to write to 8 to 9 different formal writing standards.

    If you haven’t noticed, everyone has stopped talking to you, even Pog, except me, and I do it because I think you are funny.
    kurkosdr no you the only idiot who incorrectly nit picks my english any more.
    http://mrpogson.com/2017/07/18/impeach-trump-before-he-does-any-more-damage/
    There are many recent examples of the others answering what I have wrote. They have grown out of your stupidity.

    Reality it your posts that are not getting people providing answers to kurkosdr other than me. You have it backwards.

  121. Grece says:

    Instead of waiting for chips that never materialize, just realize that soon, you can order chips via Foxconn in Wisconsin.

    MAGA

  122. kurkosdr says:

    This simple means that the no viable market line is wrong.

    How could any reasonable person guess THAT? I mean, a keyword is missing (although this is probably no big deal when speaking OhioLang™).

    Kurkosdr I bet adding : did not even cross you mind.

    Yeah, I guess anybody could figure out that a colon is missing.

    Look, I ‘ll only say this once so pay attention: People aren’t supposed to guess missing words, colons, or any other punctuation marks when they ‘re reading stuff, all these should be provided by the author: You.

    Nobody is in your head (fortunately if I might say) and nobody else shares your weird syntax rules (OhioLang™) or your weird opinions about what should be guessed when reading stuff and what not.

    If you want to keep communicating with people in English, learn how to write sentences that don’t require guessing by the reader.

    If you haven’t noticed, everyone has stopped talking to you, even Pog, except me, and I do it because I think you are funny.

    And I am almost certain things are more or less the same in real life.

    If you want to get anywhere in life, I suggest you drop the idiotic “everybody speaks English wrong except me” attitude and learn how to produce valid sentences in English. Take it as friendly advice. Nobody is going to take seriously someone who talks in a way that’s somewhere between toddler-speak and Yoda-speak.

  123. Grece says:

    Meanwhile, real IT people purchase Intel boards buy the hundreds, thinking nothing of a fantasy monopoly imagined buy a feeble old man.

  124. oiaohm says:

    Kurkosdr adding a word to my stuff is normally 100 percent wrong of the bat. This is where you screw up reading items all the time. So A is wrong.

    B is wrong its an answer in context to what Deaf Spy wrote .

    Because there is no viable market for these, that is why.
    So take above line as context
    Deaf Spy no market is wrong.
    This simple means that the no viable market line is wrong.

    I am adding commas
    Add that line you broke the context because it was not comma. If anything at that point its : as it a context line.

    So no “the” and no comma so all you changes were wrong and this is why you could not read it. Kurkosdr I bet adding : did not even cross you mind.

    When I use someone name in answer to something they wrote the words most likely will only mean something if you read what they wrote. Contextual english I have told you I write in this style before. Yet you still insist on adding commas. You can bet more often than not it will be a : after someones name not a comma with my writing style but that : is pure optional.

    So, this thing has one PCI-E slot and you have to use it for the graphics card (if any common graphics card works with it, although realistically speaking, Mr. Pog would buy a random card assuming the compatibility we enjoy in PC-compatible land streches to ARM and hope for the best).
    The emulation is so that any card works. Other wise you have to get a card with a modern EFI arch neutral firmware.

    The PCI-e issue has been a major road block and not very simple to fix. If you go back most of the reported issues over the cello was failure to get the PCI-e stuff to work. Lot of this is card initializations including the so called EFI arch neutrals at times doing stuff in x86 only ways.

    Which makes Pog’s plan to fit a network card or storage I/O card on it (again with him assuming that the compatibility we enjoy in PC-compatible land streches to ARM) completely impossible even if the damn thing did ship.

    Most sata and raid cards and network cards are find being inited by the linux kernel alone. So you can ignore from start of the firmware. Items like graphics cards not so useful if inited by the Linux kernel. So storage cards or network cards his plan covered was right.

    Or code that disallows parallel instruction execution (a = b + c, d = a + e). In any of these two cases, large code cache will don’t help you. And these cases are actually common, not like your fancy idea.
    Deaf Spy really LOL. Ever head of cpu out of order execution.

    a=b+c, d=a+c comes a=b+c d=b+c+c after cpu out of order execution has played with it it can also come warped as a=d-c with d=b+c +c.

    Remember this out of order execution rewriting what is processed depends on cache so the cpu runtime optimizer can read ahead and alter what will be executed .

    Also it really hard to write code that is 100 percent sure to always be executed in order and not made parallel in modern cpu designs as the CPU out of order is willing to process a head on a wrong assume and when it turns to be a wrong presume junk the processing.

    The branch-prediction is also not correct where modern cpu process down both side of the branch until they find out what branch is being taken then junk what ever path was wrong when the cpu does not have a guess. So a branch can break into two in cpu threads and if the branch-prediciton has a guess then it only does 1 side and takes a high hit when the picked side is wrong.

    Code cache would always get flushed for context-switches between apps
    The answer in arm and many other cpu types is no it not. That a x86 presume.
    https://events.linuxfoundation.org/sites/events/files/slides/slides_10.pdf
    Caches on arm can behave really evil.

  125. Deaf Spy says:

    That’s OS-dependent.

    Except that is it quite much also processor-dependent. Even then, only partial optimizations are possible.

    If the cache shadows the whole of physical RAM…

    Bwahahahaha! This one is good, Robert. Hey, tell us, why would someone use slow RAM at all if all of it would be size of the cache? Any sane person would just put fast memory and be done with it.

    I seriously doubt most applications would flush the cache

    Bwahahahaha! That really demonstrates how little you know of caches, Robert. Applications can’t flush the cache. An user app can just invalidate its content only if it tries to get a different data the size of the data cache or higher from memory that what it is currently working with.
    Code cache would always get flushed for context-switches between apps, because apps, you know, don’t share same code normally. Even when they do, then they are most probably on different code paths.

    If a process is slurping KB of instruction to process a few bytes of data

    And this is a very corner case, as apps process lots of data with tiny amount of instructions, compared to the size of data. Even then, code that breaks, for example, branch-prediction, would reduce performance dramatically. Or code that disallows parallel instruction execution (a = b + c, d = a + e). In any of these two cases, large code cache will don’t help you. And these cases are actually common, not like your fancy idea.

    Gee, you know a lot of real-life programming indeed. 🙂 Better stick to welding, old man.

  126. Kurkosdr says:

    There are no integrated graphics, but the PCI-E x16 slot can make for some interesting testing.

    So, this thing has one PCI-E slot and you have to use it for the graphics card (if any common graphics card works with it, although realistically speaking, Mr. Pog would buy a random card assuming the compatibility we enjoy in PC-compatible land streches to ARM and hope for the best).

    Which makes Pog’s plan to fit a network card or storage I/O card on it (again with him assuming that the compatibility we enjoy in PC-compatible land streches to ARM) completely impossible even if the damn thing did ship. Unless he planned to use the damn thing over a character terminal, but this is too insane even for Pog.

    Deaf Spy no market is wrong.

    How am I supposed to parse this?

    Option A: DeafSpy, no [the] market is wrong.

    Option B: DeafSpy, no market is wrong (aka no market can be wrong)

    Anyone with better OhioLang skills than me to tell me how this should be parsed?

    Of course, Ohiohan will whine that I am adding commas and words to his sentence and this breaks his fine complex syntax yada yada, because Ohioham cannot understand that what he writes is not valid English, and the reader is obligated to make assumptions about missing words and commas to make some kind of sense out of it.

  127. Deaf Spy wrote, “Context-switches flush the cache.”

    That’s OS-dependent. If the cache shadows the whole of physical RAM, there’s no need to flush on a context change. I seriously doubt most applications would flush the cache being used by hundreds of other processes and the OS.

    Deaf Spy also wrote, “Huge cache can’t compensate the overall slowness of the CPU in all other areas.”

    The CPU is often much faster than RAM. If a process is slurping KB of instruction to process a few bytes of data, as when evaluating some f(x), if the instructions are slurped from cache, the useful bandwidth from RAM increases until either the CPU or RAM is the bottleneck. Either way, the CPU gets more done. e.g. If the CPU can move 20gB/s, the cache 10 and RAM 5, a number-crunching application might run several times faster for not reading instructions from RAM.

  128. Deaf Spy says:

    CPUs running lots of loops/processes will benefit from larger caches to reduce bandwidth to RAM

    Wrong. Context-switches flush the cache.

    Huge cache can’t compensate the overall slowness of the CPU in all other areas.

  129. Deaf Spy wrote, “Will you please finally sit down and do some reading on how caches work and how and in what cases they improve the performance?”

    I did that in the 1980s. Basically, CPUs running lots of loops/processes will benefit from larger caches to reduce bandwidth to RAM. Many of the smartphone/controller chips have sub-MB caches while I need multiple MB. The slowest client on my LAN has a 512MB cache and an Intel CPU. Beast has a 2MB cache.

  130. oiaohm says:

    http://www.workofard.com/2017/03/project-dogfood-my-arm64-desktop/

    Deaf Spy no market is wrong. The issues that have been run into is lots. Including video cards needing x86 emulation to activate. Some things are not easy.

    Interesting part is this year we are getting to the point everything to use PCIe x16 video cards at least from system init point of view with arm64 is now working.

  131. Deaf Spy says:

    I still don’t understand why similar boards aren’t pouring forth using the new chips with decent caches…

    That is an easy one, Robert. Because there is no viable market for these, that is why.

    Your obsession with “decent caches” being the remedy for all CPU-related bottlenecks is just sweet. Will you please finally sit down and do some reading on how caches work and how and in what cases they improve the performance?

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